Optimal Wire Sizing and Bu er Insertion for Low Power and a Generalized Delay Model

We present eecient, optimal algorithms for timing optimization by discrete wire sizing and buuer insertion. Our algorithms are able to minimize a cost function subject to given timing constraints; we focus on minimization of dynamic power dissipation, but the algorithm is also easily adaptable to, for example, area minimization. In addition, the algorithm eeciently computes the complete, optimal power-delay tradeoo curve for added design exibility. An extension of our basic algorithm accommodates a generalized delay model which takes into account the eeect of signal slew on buuer delay which can contribute substantially to overall delay. This work represents the most eecient algorithms to date for the discrete wire sizing problem and for wire sizing in conjunction with buuer insertion. It is also, to the best of our knowledge, the rst work on buuer insertion to incorporate signal slew into the delay model while guaranteeing optimality. The eeectiveness of these methods is demonstrated experimentally.